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general description the ds2045 is a 1mb reflowable nonvolatile (nv) sram, which consists of a static ram (sram), an nv con- troller, and an internal rechargeable manganese lithium (ml) battery. these components are encased in a sur- face-mount module with a 256-ball bga footprint. whenever v cc is applied to the module, it recharges the ml battery, powers the sram from the external power source, and allows the contents of the sram to be mod- ified. when v cc is powered down or out of tolerance, the controller write-protects the sram? contents and powers the sram from the battery. two versions of the ds2045 are available, which provide either a 5% or 10% power-monitoring trip point. the ds2045 also contains a power-supply monitor output, rst , which can be used as a cpu supervisor for a microprocessor. applications raid systems and servers pos terminals industrial controllers data-acquisition systems gaming fire alarms router/switches plc features ? single-piece, reflowable, 27mm 2 pbga package footprint ? internal ml battery and charger ? unconditionally write-protects sram when v cc is out-of-tolerance ? automatically switches to battery supply when v cc power failures occur ? internal power-supply monitor detects power fail at 5% or 10% below nominal v cc (5v) ? reset output can be used as a cpu supervisor for a microprocessor ? industrial temperature range (-40 c to +85 c) ? ul recognized ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram ______________________________________________ maxim integrated products 1 rev 3; 5/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information pin configuration appears at end of data sheet. part temp range pin-package speed (ns) supply tolerance ds2045ab-70 -40? to +85? 256 ball 27mm 2 bga module 70 5 ds2045ab-70# -40? to +85? 256 ball 27mm 2 bga module 70 5 typical operating circuit p4.0 p3.6 p3.7 p1.0? ad0?d7 p4.4 p2.0? p3.2 rst a8?5 a0? a16 dq0? oe we ce 8 bits 8 bits 8 bits (ce0) (int0) 8051 microprocessor ds2045 128k x 8 nv sram (wr) (rd) # denotes a rohs-compliant device that may include lead that is exempt under the rohs requirements. ordering information continued at end of data sheet.
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40 c to +85 c) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on any pin relative to ground .................-0.3v to +6.0v operating temperature range ...........................-40? to +85? storage temperature range ...............................-40? to +85? soldering temperature .....................see ipc/jedec j-std-020 parameter symbol conditions min typ max units ds2045ab 4.75 5.25 supply voltage v cc ds2045y 4.50 5.50 v input logic 1 v ih 2.2 v cc v input logic 0 v il 0 0.8 v capacitance (t a = +25 c) parameter symbol conditions min typ max units input capacitance c in not tested 7 pf input/output capacitance c out not tested 7 pf dc electrical characteristics (v cc = 5v ?% for ds2045ab, v cc = 5v ?0% for ds2045y, t a = -40 c to +85 c.) parameter symbol conditions min typ max units input leakage current i il -1.0 +1.0 a i/o leakage current i io ce = v cc -1.0 +1.0 a output-current high i oh at 2.4v -1.0 ma output-current low i ol at 0.4v 2.0 ma output-current low rst i ol rst at 0.4v (note 1) 10.0 ma i ccs1 ce = 2.2v 0.5 7 standby current i ccs2 ce = v cc - 0.5v 0.2 5 ma operating current i cco1 t rc = 200ns, outputs open 85 ma ds2045ab 4.50 4.62 4.75 write protection voltage v tp ds2045y 4.25 4.37 4.50 v
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram _____________________________________________________________________ 3 power-down/power-up timing (t a = -40 c to +85 c) parameter symbol conditions min typ max units v cc fail detect to ce and we inactive t pd (note 7) 1.5 ? v cc slew from v tp to 0v t f 150 ? v cc slew from 0v to v tp t r 150 ? v cc valid to ce and we inactive t pu 2ms v cc valid to end of write protection t rec 125 ms v cc fail detect to rst active t rpd (note 1) 3.0 ? v cc valid to rst inactive t rpu (note 1) 225 350 525 ms data retention (t a = +25 c) parameter symbol conditions min typ max units expected data-retention time (per charge) t dr (note 8) 2 3 years ac electrical characteristics (v cc = 5v ?% for ds2045ab, v cc = 5v ?0% for ds2045y, t a = -40 c to +85 c.) ds2045ab-70 DS2045Y-70 ds2045ab-100 ds2045y-100 parameter symbol conditions min max min max units read cycle time t rc 70 100 ns access time t acc c l = 100pf 70 100 ns oe to output valid t oe 35 50 ns ce to output valid t co 70 100 ns oe or ce to output active t coe (note 2) 5 5 ns output high impedance from deselection t od (note 2) 25 35 ns output hold from address change t oh 55ns write cycle time t wc 70 100 ns write pulse width t wp (note 3) 55 75 ns address setup time t aw 00ns t wr1 (note 4) 5 5 write recovery time t wr2 (note 5) 15 15 ns output high impedance from we t odw (note 2) 25 35 ns output active from we t oew (note 2) 5 5 ns data setup time t ds (note 6) 30 40 ns t dh1 (note 4) 0 0 data hold time t dh2 (note 5) 10 10 ns
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram 4 _____________________________________________________________________ read cycle output data valid t rc t acc t co t oe t oh t od t od t coe t coe v ih v ih v il v oh v ol v oh v ol v il v ih addresses ce oe d out (see note 9.) v ih v ih v ih v ih v il v il v il
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram _____________________________________________________________________ 5 write cycle 1 data in stable addresses ce we d out d in t wc v ih v ih v ih v ih v il v il v il high impedance v ih v ih v il v il v ih v il v il v il v il t aw t wp t oew t dh1 t ds t odw t wr1 (see notes 2, 3, 4, 6, 10?3.) write cycle 2 t wc t aw t dh2 t ds t coe t odw t wp t wr2 v ih v il v ih addresses ce we d out d in v il v ih v il v ih v il v il v il v il v ih v ih v il v ih data in stable v il v ih v il (see notes 2, 3, 5, 6, 10e13.)
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram 6 _____________________________________________________________________ power-down/power-up condition t dr t pu t f t pd t rpu t rpd slews with v cc t r v ol v ih v ol t rec v cc v tp ~2.7v ce, we rst backup current supplied from lithium battery (see notes 1, 7.) note 1: rst is an open-drain output and cannot source current. an external pullup resistor should be connected to this pin to real- ize a logic-high level. note 2: these parameters are sampled with a 5pf load and are not 100% tested. note 3: t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. note 4: t wr1 and t dh1 are measured from we going high. note 5: t wr2 and t dh2 are measured from ce going high. note 6: t ds is measured from the earlier of ce or we going high. note 7: in a power-down condition, the voltage on any pin can not exceed the voltage on v cc . note 8: the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. minimum expected data-retention time is based on a maximum of two 230? convection solder reflow exposures, followed by a fully charged cell. full charge occurs with the initial application of v cc for a minimum of 96 hours. this para- meter is assured by component selection, process control, and design. it is not measured directly in production testing. note 9: we is high for a read cycle. note 10: oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. note 11: if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high- impedance state during this period. note 12: if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high- impedance state during this period. note 13: if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high-impedance state during this period. note 14: ds2045 bga modules are recognized by underwriters laboratory (ul) under file e99151.
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram _____________________________________________________________________ 7 supply current vs. operating frequency ds2045 toc01 v cc (v) supply current (ma) 5.5 5.0 4.5 5 10 15 20 25 0 4.0 6.0 5mhz 100% duty cycle 5mhz 50% duty cycle 1mhz 100% duty cycle 1mhz 50% duty cycle t a = +25 c supply current vs. supply voltage ds2045 toc02 v cc (v) supply current ( a) 5.5 5.0 4.5 160 170 180 190 200 210 220 230 240 250 150 4.0 6.0 t a = +25 c battery charger current vs. battery voltage ds2045 toc03 delta below v chrg (v) battery charger current, i chrg (ma) 0.6 0.8 0.4 0.2 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0 01.0 v cc = ce = 5.0v v chrg v chrg percent change vs. temperature ds2045 toc04 temperature ( c) v chrg percent change from +25 c (%) 80 70 50 60 -10 0 10 20 30 40 -30 -20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 -40 v cc = 5.0v v bat = v chrg v tp vs. temperature ds2045 toc05 temperature ( c) write protect, v tp (v) 80 60 20 40 0 -20 4.30 4.35 4.40 4.45 4.50 4.55 4.60 4.65 4.70 4.75 4.25 -40 ds2045ab ds2045y dq i oh vs. dq v oh ds2045 toc06 i oh (ma) v oh (v) -1 -2 -3 -4 3.7 3.9 4.1 4.3 4.5 4.7 4.9 3.5 -5 0 v cc = 4.5v dq i ol vs. dq v ol ds2045 toc07 i ol (ma) v ol (v) 4.5 4.0 0.5 1.0 1.5 2.5 3.0 2.0 3.5 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 05.0 v cc = 4.5v rst output-voltage low vs. output-current low ds2045 toc08 i ol (ma) v ol (v) 15 10 5 0.1 0.2 0.3 0.4 0.5 0 020 v cc = 4.25v rst voltage vs. v cc during power-up ds2045 toc09 v cc power-up (v) rst voltage w/pullup resistor (v) 5.0 4.5 3.5 4.0 1.0 1.5 2.0 2.5 3.0 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 05.5 ds2045ab t a = +25 c typical operating characteristics (v cc = +5.0v, t a = +25 c, unless otherwise noted.)
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram 8 _____________________________________________________________________ balls name description a1, a2, a3, a4 gnd ground b1, b2, b3, b4 n.c. no connection c1, c2, c3, c4 a15 address input 15 d1, d2, d3, d4 a16 address input 16 e1, e2, e3, e4 rst open-drain reset output f1, f2, f3, f4 v cc supply voltage g1, g2, g3, g4 we write enable input h1, h2, h3, h4 oe output enable input j1, j2, j3, j4 ce chip enable input k1, k2, k3, k4 dq7 data input/output 7 l1, l2, l3, l4 dq6 data input/output 6 m1, m2, m3, m4 dq5 data input/output 5 n1, n2, n3, n4 dq4 data input/output 4 p1, p2, p3, p4 dq3 data input/output 3 r1, r2, r3, r4 dq2 data input/output 2 t1, t2, t3, t4 dq1 data input/output 1 u1, u2, u3, u4 dq0 data input/output 0 v1, v2, v3, v4 gnd ground w1, w2, w3, w4 gnd ground y1, y2, y3, y4 gnd ground a17, a18, a19, a20 gnd ground b17, b18, b19, b20 n.c. no connection c17, c18, c19, c20 n.c. no connection d17, d18, d19, d20 a14 address input 14 e17, e18, e19, e20 a13 address input 13 f17, f18, f19, f20 a12 address input 12 g17, g18, g19, g20 a11 address input 11 h17, h18, h19, h20 a10 address input 10 j17, j18, j19, j20 a9 address input 9 k17, k18, k19, k20 a8 address input 8 l17, l18, l19, l20 a7 address input 7 m17, m18, m19, m20 a6 address input 6 balls name description n17, n18, n19, n20 a5 address input 5 p17, p18, p19, p20 a4 address input 4 r17, r18, r19, r20 a3 address input 3 t17, t18, t19, t20 a2 address input 2 u17, u18, u19, u20 a1 address input 1 v17, v18, v19, v20 a0 address input 0 w17, w18, w19, w20 gnd ground y17, y18, y19, y20 gnd ground a5, b5, c5, d5 n.c. no connection a6, b6, c6, d6 n.c. no connection a7, b7, c7, d7 n.c. no connection a8, b8, c8, d8 n.c. no connection a9, b9, c9, d9 n.c. no connection a10, b10, c10, d10 n.c. no connection a11, b11, c11, d11 n.c. no connection a12, b12, c12, d12 n.c. no connection a13, b13, c13, d13 n.c. no connection a14, b14, c14, d14 n.c. no connection a15, b15, c15, d15 n.c. no connection a16, b16, c16, d16 n.c. no connection u5, v5, w5, y5 n.c. no connection u6, v6, w6, y6 n.c. no connection u7, v7, w7, y7 n.c. no connection u8, v8, w8, y8 n.c. no connection u9, v9, w9, y9 n.c. no connection u10, v10, w10, y10 n.c. no connection u11, v11, w11, y11 n.c. no connection u12, v12, w12, y12 n.c. no connection u13, v13, w13, y13 n.c. no connection u14, v14, w14, y14 n.c. no connection u15, v15, w15, y15 n.c. no connection u16, v16, w16, y16 n.c. no connection pin description
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram _____________________________________________________________________ 9 functional diagram current-limiting resistor battery-charging/shorting protection circuitry (ul recognized) redundant logic delay timing circuitry charger current-limiting resistor v tp ref v sw ref gnd ml ce rst ce redundant series fet sram dq0? oe we v cc v cc uninterrupted power supply for the sram ds2045 oe we a0?16 detailed description the ds2045 is a 1mb (128k x 8 bits) fully static, nv memory similar in function and organization to the ds1245 nv sram, but containing a rechargeable ml battery. the ds2045 nv sram constantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. there is no limit to the number of write cycles that can be executed and no additional support circuitry is required for microproces- sor interfacing. this device can be used in place of sram, eeprom, or flash components. the ds2045 assembly consists of a low-power sram, an ml battery, and an nv controller with a battery charger, integrated on a standard 256-ball, 27mm 2 bga substrate. unlike other surface-mount nv memory modules that require the battery to be removable for soldering, the internal ml battery can tolerate exposure to convection reflow soldering temperatures allowing this single-piece component to be handled with stan- dard bga assembly techniques. two versions of the ds2045 are available that provide either a 5% (ds2045ab) or 10% (ds2045y) power- monitoring trip point. the ds2045 also contains a power-supply monitor output, rst , which can be used as a cpu supervisor for a microprocessor.
ds2045y/ab read mode the ds2045 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address specified by the 17 address inputs (a0 to a16) defines which of the 131,072 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later occurring sig- nal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds2045 executes a write cycle whenever the ce and we signals are active (low) after address inputs are stable. the later-occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inac- tive (high) during write cycles to avoid bus contention. however, if the output drivers have been enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data-retention mode the ds2045ab provides full functional capability for v cc greater than 4.75v and write-protects at 4.5v. the ds2045y provides full functional capability for v cc greater than 4.5v and write-protects at 4.25v. data is maintained in the absence of v cc without additional support circuitry. the nv static ram constantly moni- tors v cc . should the supply voltage decay, the nv sram automatically write-protects itself. all inputs become ?on? care? and all data outputs become high impedance. as v cc falls below approximately 2.7v (v sw ), the power-switching circuit connects the lithium energy source to the ram to retain data. during power- up, when v cc rises above v sw , the power-switching circuit connects external v cc to the ram and discon- nects the lithium energy source. normal ram operation can resume after v cc exceeds v tp for a minimum duration of t rec . battery charging when v cc is greater than v tp , an internal regulator charges the battery. the ul-approved charger circuit includes short-circuit protection and a temperature-sta- bilized voltage reference for on-demand charging of the internal battery. typical data-retention expectations of 3 years per charge cycle are achievable. a maximum of 96 hours of charging time is required to fully charge a depleted battery. system power monitoring when the external v cc supply falls below the selected out-of-tolerance trip point, the output rst is forced active (low). once active, the rst is held active until the v cc supply has fallen below that of the internal bat- tery. on power-up, the rst output is held active until the external supply is greater than the selected trip point and one reset timeout period (t rpu ) has elapsed. this is sufficiently longer than t rec to ensure that the sram is ready for access by the microprocessor. freshness seal and shipping the ds2045 is shipped from dallas semiconductor with the lithium battery electrically disconnected, guarantee- ing that no battery capacity has been consumed during transit or storage. as shipped, the lithium battery is ~60% charged, and no preassembly charging opera- tions should be attempted. when v cc is first applied at a level greater than v tp , the lithium battery is enabled for backup operation. a 96 hour initial battery charge time is recommended for new system installations. ds2045y/ab single-piece 1mb nonvolatile sram 10 ____________________________________________________________________ memory operation truth table x = don? care. we ce oe mode i cc outputs 1 0 0 read active active 1 0 1 read active high impedance 0 0 x write active high impedance x 1 x standby standby high impedance
recommended cleaning procedures the ds2045 may be cleaned using aqueous-based cleaning solutions. no special precautions are needed when cleaning boards containing a ds2045 module. removal of the topside label violates the environmen- tal integrity of the package and voids the warranty of the product. applications information power-supply decoupling to achieve the best results when using the ds2045, decouple the power supply with a 0.1? capacitor. use a high-quality, ceramic surface-mount capacitor if pos- sible. surface-mount components minimize lead induc- tance, which improves performance, while ceramic capacitors have adequately high frequency response for decoupling applications. using the open-drain rst output the rst output is open drain, and therefore requires a pullup resistor to realize a high logic output level. pullup resistor values between 1k ? and 10k ? are typical. battery charging/lifetime the ds2045 charges an ml battery to maximum capacity in approximately 96 hours of operation when v cc is greater than v tp . once the battery is charged, its lifetime depends primarily on the v cc duty cycle. the ds2045 can maintain data from a single, initial charge for up to 3 years. once recharged, this deep- discharge cycle can be repeated up to 20 times, pro- ducing a worst-case service life of 60 years. more typical duty cycles are of shorter duration, enabling the ds2045 to be charged hundreds of times, therefore extending the service life well beyond 60 years. ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram ____________________________________________________________________ 11 note: all temperatures refer to top side of the package, mea- sured on the package body surface. profile feature sn-pb eutectic assembly average ramp-up rate (t l to t p ) 3 c/second max preheat - temperature min (t smin ) - temperature max (t smax ) - time (min to max) (ts) 100 c 150 c 60 to 120 seconds t smax to t l - ramp-up rate time maintained above: - temperature (t l ) - time (t l ) 183 c 60 to 150 seconds peak temperature (t p ) 225 +0/-5 c time within 5 c of actual peak temperature (t p ) 10 to 30 seconds ramp-down rate 6 c/second max time 25 c to peak temperature 6 minutes max recommended reflow temperature profile ordering information (continued) part temp range pin-package speed (ns) supply tolerance ds2045ab-100 -40? to +85? 256 ball 27mm 2 bga module 100 5 ds2045ab-100# -40? to +85? 256 ball 27mm 2 bga module 100 5 DS2045Y-70 -40? to +85? 256 ball 27mm 2 bga module 70 10 DS2045Y-70# -40? to +85? 256 ball 27mm 2 bga module 70 10 ds2045y-100 -40? to +85? 256 ball 27mm 2 bga module 100 10 ds2045y-100# -40? to +85? 256 ball 27mm 2 bga module 100 10 # denotes a rohs-compliant device that may include lead that is exempt under the rohs requirements.
ds2045y/ab ds2045y/ab single-piece 1mb nonvolatile sram maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products. is a registered trademark of dallas semiconductor corporation. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . pin configuration a 12 34 789 0 5 6 7 8 90 1 2 34 56 1 2 34 1 1 1 2 5 678 9 1 1 1 1 1 1 1 11 1 2 1 1 1 11 1 1 7 8 9 0 0 1 2 3 4 5 6 ds2045 b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y top view gnd n.c. a15 a16 rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd gnd gnd gnd n.c. n.c. a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd gnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c.

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